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System-On-Chip Solutions For Portable Medical Devices

DESIGN 

System-On-Chip Solutions For Portable Medical Devices
 
A dedicated system-on-chip (SoC) integrates as much functionality as possible in a single chip and thereby allows miniaturisation of portable medical systems, while optimising performance and power consumption. Today’s feature-rich semiconductor process technology platforms mean that SoC based solutions also optimise the cost and reliability of the overall system by reducing the number of components that are employed.
 
D. Manic, D. Severac, M. Morgan, and J.-P. Dan
CSEM, Swiss Centre for Electronics and Microtechnology, Neuchâtel, Switzerland

 Facts and needs

Image: iStockPhoto
An ever increasing number of devices are becoming portable. In the medical domain, devices for health monitoring, health telemetry and drug delivery systems are well known examples of these growing groups of implantable or portable devices. The nature of these devices has significant implications for their technology as follows.

  • Without a power cord, most of these devices rely on a battery and power consumption has a direct effect on the autonomy of the device.
  • There is a constant demand for more features, higher performance, lower cost, better reliability and a reduction in size and weight.
  • The higher performance requirements of portable medical devices demand more data processing power and improved networking capability.
  • Some medical device applications such as implantable devices may impose demanding constraints on device form factor (size and shape) and reliability.

Semiconductor technology and its advances driven by mobile phone and consumer electronic applications enable interesting product development opportunities for portable medical applications. The following discussion examines how a system-on-chip (SoC) approach successfully fulfills the requirements outlined above.

The technical answer

Over several decades, the electronics industry has evolved from solutions with discrete components to solutions that integrate ever more functionality and flexibility. The field-programmable gate array (FPGA) semiconductor device offers suitable time to market, but is far from being optimal for power consumption, performance, integration of analogue functions and overall form factor.

Table I. (click to enlarge) The main advantages of ASIC SoCs.
The industry offers two types of SoC: an off-the-shelf standard chip, the application specific standard product (ASSP); and a custom-made chip, the application specific integrated circuit (ASIC). ASSPs offer a well adapted solution when the marketability of a platform of common shared specifications has been identified. However, the technical arguments in favour of an ASIC SoC for medical applications are numerous. The main advantages are listed in Table I.

Figure 1. (click to enlarge) Example of SoC architecture.
This article focuses on ASIC SoCs, which allow true flexibility, and emphasises the advantages of custom SoCs for medical device applications. Figure 1 shows an example of this SoC architecture. Using this for medical device applications helps to fulfill the aforementioned requirements.1

An economic solution

Figure 2. (click to enlarge) Production quantity vs. chip costs for comparable ASIC and FPGA solutions.
Despite the advantages over the other solutions, some professionals still hesitate in adopting ASIC SoC technology. Their main concern is usually the cost. However, there has been progress in several aspects of the technology, thus, the cost issue is often based on misconceptions rather than informed decisions. Figure 2 compares the chip costs of solutions based on an ASIC SoC with a FPGA. The comparison uses a leading FPGA on the market, which claims to replace ASICs and ASSPs in many applications, including networking, telecommunications, computing, wireless and medical applications. Note that a FPGA or ASSP SoC solution may not always be applicable depending on the specifications of the application. The cost of 3000 chips for the ASIC SoC based solution, including nonrecurring expenses (NRE) for a standard design using 0.18 µm complementary metal oxide semiconductor (CMOS) technology, is comparable to that of a FPGA solution. This is because of the smaller silicon area of the ASIC combined with present day low volume production offered by silicon foundries (for example, multiproject wafers, multilayer lithographic masks). Beyond a certain production volume, that is, 6000 units, the use of full lithographic masks dramatically reduces the cost per chip.

The breakeven point depends heavily on the NRE, which can be divided into three major components: design effort, tooling of the lithographic masks to produce the chips, and qualification of the chips. Today, the reuse of existing intellectual property blocks and advances in electronic design automation tools greatly shorten the design process and the qualification of a chip. SoCs can be designed and qualified in less than two person years.

In addition to the above mentioned cost comparison between the ASIC and FPGA approaches, the potential for cost-effectiveness of medical device design based on SoCs is much greater. Thanks to the advantages provided by SoCs, a careful system design yields a highly optimised cost for the overall production of the final application system. This cost reduction can be achieved by reducing the number of components, and implementing a built-in self test and long term product evolution.
Moreover, adding features such as miniaturisation, portability, robustness, reliability, customisation, exclusivity and intellectual property protection brings major assets to the company that is first to place a custom SoC based solution on the market.

Low power SoC example

Figure 3. (click to enlarge) WiseNet SoC in TSMC 0.18 µm technology. This low-power chip combines subgigahertz radio transceiver, an 8-bit microcontroller, memories (SRAM and ROM), complex power management, AD converter and sensor interface on 11.88 mm2 of silicon surface.
The concrete realisation of an ASIC SoC is shown in Figure 3. This comprises a complex, low power, low voltage chip that combines subgigahertz radio transceiver, a digital processing part with an 8-bit low-power microcontroller (CoolRISC), read only memory (ROM) and special low-leakage static random access memories (SRAM), power management, an analogue to digital converter (ADC) and a sensor interface on less than 12 mm2. The thickness of the die typically ranges from 200–300 µm. This SoC consists of 1.7 million transistors, 1906 resistors, 341 capacitors and 8 inductors. To illustrate the achieved performance, the SoC runs at 0.9–1.5 V, has a 10-bit ADC for sensor interfacing, consumes 2 mA when receiving, 30 mA when transmitting and 25 µA on average (running at a duty cycle of power up to sleep mode of 0.1–1.0%). The maximum radio data rate is 100 kb/s. More details about this SoC can be found in the literature.2

This ASIC SoC example is not dedicated to medical applications, but is part of a technology platform that targets short range and low data rate applications within wireless sensor networks in general. However, this technology platform is typically used for portable medical systems.

Other medical applications may require more powerful processors for signal processing, for example, for electrocardiogram analysis, hearing aids, data compression or encryption. The icyflex produced by CSEM is an example of this type of processor. It offers advanced data crunching capability for embedded devices, including digital signal processor (DSP) style 32-bit data paths and a high level of parallelism, a C compiler and on-chip debugging capability at a low power consumption of less than 200 µW per MHz of processor clock speed.

The backbone of a low-power SoC is an energy efficient processor, however the overall circuit architecture needs low power consumption design expertise as well as low power libraries such as SRAM, ROM and nonvolatile memories. More information on low-power electronics design is available in the literature.3

Further power optimisation and miniaturisation of a wireless SoC is possible by using new radio transceiver architectures based on bulk acoustic wave and microelectromechanical systems (silicon resonators).4

An exclusive solution

SoC based solutions are now an interesting option for medical device applications. They bring together a maximum amount of functionality in reduced volume, optimise the system performance and reduce the power consumption. They optimise the cost-effectiveness and reliability of the overall system by reducing the number of components involved. The return on investment can be high with production starting as low as a few thousand chips. SoCs offer the added bonus of a customised and exclusive solution.

 


References

1. J. Weiland, “System-on-Chip Solutions For Next-Generation Medical Applications,” Medical Electronics Manufacturing (Autumn 2003).

2. V. Peiris, “WiseNET, An Ultra Low-Power RF Transceiver SoC and Communication Protocol Solution for Wireless Sensor Networks,” A.H. M. van Roermund, H. Casier, M. Steyaert, Eds., Advances in Analog Circuit Design (AACD) – High-Speed A-D Converters, Automotive Electronics and Ultralow Power Wireless, 345–376, Edition Springer, Berlin, Germany (2006).

3. Low-Power Electronics Design, Ed. C. Piguet, CRC Press LLC, Boca Raton, Florida, USA (2005).

4. C. Enz et al., “Ultra Low-Power MEMS-Based Radio For Wireless Sensor Networks,” Proc. of the 2007 European Conference on Circuit Theory and Design, 320–331, Seville, Spain (August 2007).

 
Dr Dragan Manic is Product Manager and Dr Daniel Severac is Project Manager both in the Microelectronics Division, Marc Morgan is Head of the Digital and SoC Design, and Jean-Pierre Dan is Senior Manager, Business Development, at CSEM, Swiss Centre for Electronics and Microtechnology, Rue Jaquet-Droz 1, CH-2002 Neuchâtel, Switzerland, tel. +41 32 720 5111, e-mail: dragan.manic@csem.ch,www.csem.ch/fs/microelectronics.htm

 

Source:    Dr Dragan Manic, Dr Daniel Severac, Marc Morgan, and Jean-Pierre Dan,
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